1. Field of the Invention
This invention relates to a communication control unit for a local area network. More particularly, it relates to a communication control unit which has a first and a second communication control means in order to execute higher and lower protocol layers separately.
2. Description of the Prior Art
Recently, communication control units, which are used in local area networks, have been decreased in size using the LSI technique. As the control of a MAC (Medium Access Control) layer has been carried out using LSIs, communication control units have become widely used, especially in the token ring system and the token bus system specified by IEEE standards.
As a result, a communication control unit in which MAC sublayer data and LLC (Logical link control) sublayer data are separately buffered, has been developed. MAC sublayer data (referred to as a MAC frame, below) should be processed inside the communication control unit which is made of LSIs, while LLC sublayer data (referred to as a LLC frame, below) should be processed in a higher layers control unit.
For example, in our report VLSI architecture for an IEEE 802.5 token-ring LAN controller", Tanaka et al., Custom Integrated Circuit Conference, 1989, a token-ring LAN control unit (TRC) which has two 128 byte FIFOs as buffers only for LLC frames and three FIFOs (two of which have 128 bytes and another has 40 bytes) as buffers only for MAC frames, is reported. Thus, the communication control unit is workable only for the MAC layer process because of the separation of buffers as described in this report.
On the other hand, in order to process communication data easier in a higher layers control unit, LLC frames should not be stored in a continuous memory area, but should be stored in divided memory areas (frame buffer areas, or FBs), each of which is comprised of tens to thousands of bytes. (This data structure is shown in FIG. 4 and the detail will be described in the explanation of embodiments.) Thus, if one unit is comprised of 128 bytes, an LLC frame having 10 K bytes is stored dividedly in 80 FBs. In order to gather up the data which are distributed into a plurality of FBs as mentioned above, a new data structure called the frame discriptor (FD) is used. This FD contains the whole length of an LLC frame, an FB address in which the beginning of the LLC frame is stored, their statuses, and so on. As a result, the communication control unit should not handle only the read-out of received data. The real operation of this LLC frame is as follows.
In a communication control unit, an FB list and an FD list are provided in advance to be used for receiving. When an LLC frame is received, DMA device begins to work under the control of a CPU which is incorporated in this control unit, so as to break up the LLC frame into a buffer size when it is transferred into buffers registered in the FB list. CPU sets an FD with the frame length, the FB address, and the status at the receiving end, and informs the higher layers control unit of these data through interrupt signals. In the case where a MAC frame is received, CPU descriminates the frame type. In other words, if the frame is found to be one which should be transferred to the higher layers control unit, it is processed in the same way as an LLC frame. Also, if the frame is found to be one which should be processed inside the unit, it is not written into memories.
According to the above mentioned structure of the prior art communication control unit, information regarding not only communication data but also various control data should be stored into memories. However, a usual DMA device cannot carry out such processes. So, those processes must be carried out in the CPU. Also, the final judgement regarding which frame must be stored into memories, should be carried out in the CPU. In the past, communication speeds were slow, so that the process time in the CPU did not have problems, because the time interval of receiving frames was relatively long. Recently, however, communication speeds have become faster and a large number of frames are received one after another. So, a reatively large time lag has arisen in the CPU process. According to this time lag, the activation of the DMA and the assignment of buffers occurs late. As a result, frames sometimes could not be received correctly by the communication control unit. In a TRC, for example, usually two FIFOs are provided for LLC frames. In this device, when a first frame has been received completely, the data are stored into the first FIFO. If a second frame is received during the output of the data from the first FIFO into memories, the data from the second frame are stored in the second FIFO. After the output from the first FIFO has been completed, the contents of the second FIFO is output. Thus, the continuous receiving of frames can be carried out in the TRC, using the two FIFOs alternatively. In this case, however, if the output from the second FIFO is late for the completion time of output from the first FIFO, the second FIFO overflows the data to cause a reception failure. Also, if the releasing of data from the first FIFO and the preparation for receiving the third frame are late, this third frame cannot be received at all by the first FIFO. Especially, in the case where short frames are received continuously, the handling interval requires a time shorter than the processing time, thus frequently causing receiving failures. In order to cope with this problem, increasing the number of FIFOs can be considered. It is, however, not a good solution because the increase of FIFOs requires the control circuit to become complicated and increase in size.